1. Field of the Invention
This invention relates to a method for routing electrical connections between components on an integrated substrate or on an interconnection board and the resulting product. Electrical interconnections of the individual components on large or very large scale integrated circuit and interconnection packages are achieved using metallic wiring paths between points (or pins) to be connected. Each set of pins to be interconnected, and by extension, the wiring paths connecting those points are call a net. When the net is separated into routings from pin-to-pin, the individual pin-to-pin parts of the nets are called connections. It is possible in some schemes for the wiring path to be part of more than one connection. The paths are formed on one or more surfaces called planes (also referred to as "wiring planes" or "signal planes"). Several planes make up the substrate or board. Connections are usually decomposed into a sequence of horizontal, vertical and inter-plane segments. Usually the vertical wire path segments, i.e., those travelling parallel to the y-axis, are predominantly located on one or more planes labelled the "y" planes; while horizontal wire path segments, i.e., those travelling parallel to the x-axis, are predominantly located on different planes, labelled "x" planes. The preferred direction of wiring in a plane is in a direction parallel to the axis of that plane. Each potential wiring path site on a plane is referred to as a "track". The wire segments, etched or drilled, between planes are called vias. Vias can be of two types: thru vias and partial (or segmented) vias. Thru vias pass thru the entire board, and thus permit interconnection of wire segments on any planes of the board. Thru vias are often identical to the holes thru which the pins of the components are mounted on the board. Partial vias exist in two forms: (1) a link between arbitrary planes of length the distance between the planes, or (2) a link between certain adjacent planes. Two signal planes having angularly disposed wiring tracks, and particularly when linked by partial vias, are referred to as a "plane-pair".
A signal plane may have one or more "escape regions". The remainder of the plane is referred to as the "global region". An escape region differs from the global region in that it is a contiguous area whose boundary coincides with the rectangle enclosing the pins of one or possibly more components mounted (or to be mounted) on the board. The work "pins" is used here in the sense of end points of connections. An area encompassing a dense set of test points or the area encompassing the points of exit from the board are escape regions.
Possibly associated with an escape region is an "escape problem". An escape problem exists when the number of connections which must enter or leave an escape region to connect to pins within the escape region approaches or exceeds the number of tracks which cross the perimeter of the escape region, counting only tracks in each plane's preferred routing direction. When an escape problem exists, the wire routing methods which are successful in the global region will not be successful in the escape region. With the recent advent of large components having many pins, the connection to pins within an escape region can be dominant over the connection between escape regions in determining the number of planes required to complete the wiring. The present invention relates to a method and resulting pattern for reducing the number of planes when escape problems determine the number of planes required.
2. Description of the Prior Art
The prior art solutions to the escape problem are: (1) avoid routing wires that do not connect to the component's pins; (2) increase the number of planes; (3) customize (for each component) an "escape pattern" out to a distance beyond the component where there are sufficient tracks for all interconnections to be continued by the normal routing strategy; and (4) specify an escape pattern that is the same for all similar components out to a sufficiently large distance as in (3).
The creation of a custom escape pattern for each component usually involves manual effort, increased turn-around time, and the risk of error. The use of a predefined escape pattern avoids the time and the potential for error after the initial definition, but all possible connections must be made, usually increasing the number of paths in the area. If only a single electrical connection per pin is brought to the perimeter, there may be a degradation of electrical performance for high-speed transitions if the net is not point-to-point but rather contains intermediate receivers. Further, the direction of the escape path within the escape pattern is random and therefore not optimized with respect to the overall direction of the net of which it is a part.
U.S. Pat. No. 3,567,914 issued Mar. 2, 1971 to Neese et al entitled: "Automated Manufacturing System", pertains to a wire routing apparatus which takes into account certain routing penalties for finding the most desirable route available for a particular path.
U.S. Pat. No. 4,320,438 issued Mar. 16, 1982, to Ibrahim et al, entitled "Multi-layer Ceramic Package" pertains to increasing component density in an interconnection package by assigning the pins of a component to different signal planes.
IBM "Technical Disclosure Bulletin", Volume 13, No. 8, January 1971, page 2436 describes a method of increasing packing density of monolithic storage chips by using time multiplexing techniques which result in fewer wires connected to the chip.
IBM "Technical Disclosure Bulletin", Volume 24, No. 11a, April 1982, pages 5558-5560 describes a semiconductor package having a minimum of wiring layers as a result of assignment of specified functions to particular signal planes.